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1 10/02/98 sigmatel, inc. integrating mixed-signal solutions STAC9704/7 multimedia audio codec for ac?97 general description: sigmatel? s STAC9704/07 is a general purpose 18-bit, full duplex, audio codec that conforms to the analog component specification of ac?97 (audio codec ?97 component specification rev. 1.03). the STAC9704/07 incorporates sigmatel?s proprietary sigma-delta technology to achieve signal quality in excess of 95db snr. the dacs, adcs, and mixers are integrated with analog i/os, which include four analog line-level stereo inputs, two analog line-level mono inputs, and 3 output channels. also included are sigmatel?s 3d stereo enhancement ( ss3d ) and an extra true line-level out for headphones or speaker amplifiers. the STAC9704/07 communicates via the five wire ac link to any digital component of ac?97 providing flexibility in the audio system design. packaged in a small ac?97 compliant 48-pin tqfp, the STAC9704/07 can be placed on the motherboard, daughter boards, add-on cards, pcmcia cards, or outside the main chassis such as in a speaker. the 9707 is identical to the 9704 except that the 9707 is tested at avdd = dvdd = 3.3v. features: high performance s s d d technology 18-bit full duplex stereo a/d, d/a ac-link protocol compliance single power source from 5v to 3.3v ac'97 compliant mixer sigmatel surround (ss3d) stereo enhancement energy saving power down modes 48k sample/second rate six analog line-level inputs 48-pin tqfp snr > 95 db through mixer and dac stac9707 is the 3.3 volt version
2 10/02/98 ordering information: part number package temperature range supply range STAC9704t 48-pin tqfp 7mm x 7mm x 1.4mm 0 o c to +70 o c dvdd = 3.3v ? 5v, avdd = 5v stac9707t 48-pin tqfp 7mm x 7mm x 1.4mm 0 o c to +70 o c dvdd = 3.3v avdd = 3.3v sigmatel reserves the right to change specifications without notice.
sigmatel, inc STAC9704/7 3 10/02/98 table of contents general description 1 ordering information 2 1. pin/signal descriptio ns 8 1.1 digital i/o 8 1.2 analog i/o 9 1.3 filter and voltage references 10 1.4 power and ground signal s 11 2. ac-link 11 2.1 clocking 12 2.2 reset 12 3. digital interface 12 3.1 ac-link digital serial interface protocol 12 3.1.1 ac-link audio output frame (sdata_out) 14 3.1.1.1 slot 1: command address port 16 3.1.1.2 slot 2: command data port 16 3.1.1.3 slot 3: pcm playback left channel 16 3.1.1.4 slot 4: pcm playback right channel 17 3.1.1.5 slots 5-12: reserved. 17 3.1.2 ac-link audio input frame (sdata_in) 17 3.1.2.1 slot 1: status address port 19 3.1.2.2 slot 2: status data port 19 3.1.2.3 slot 3: pcm record left channel 19 3.1.2.4 slot 4: pcm record right channel 19 3.1.2.5 slots 5-12: reserved 20 3.2 ac-link low power mode 20 3.2.1 waking up the ac-link 21 4. STAC9704/7 mixer 21 4.1 mixer input. 2 3 4.2 mixer output 23 4.3 pc beep implementations 23 4.4 mixer registers 24 4.4.1 reset register 25 4.4.2 play master volume registers 25 4.4.3 pc beep register 25 4.4.4 analog mixer input gain 26 4.4.5 record select control 26 4.4.6 record gain registers 28 4.4.7 general purpose register 28 4.4.8 3d control register 29 4.4.9 powerdown control/status 29 5. low power modes 30 6. testability 32 7. ac timing characteristics 32 7.1 cold reset. 32 7.2 warm reset 33 7.3 clocks 34 7.4 data setup and hold 35 7.5 signal rise and fall times 36 7.6 ac-link low power mode timing 36 7.7 ate test mode 37 8. electrical specifications 38 8.1 absolute maximum ratings 38 8.2 recommended operating conditions 38 8.3 power consumption 39 8.4 ac link static digital specifications 39 8.5 9704 analog performance characteristics 40 8.6 9707 analog performance characteristics 42 appendix a 44 appendix b 45
sigmatel, inc STAC9704/7 4 10/02/98 table of contents ? tables table 1 ? package dimensions 5 table 2 ? pin designation 5 table 3 ? digital signal list 8 table 4 ? analog signal list 9 table 5 ? filtering and voltage references 10 table 6 ?power signal list STAC9704/07 11 table 7 table 8 ? mixer functional connections 22 table 9 ? mixer registers 24 table 10 ? play master volume register 25 table 11 ? pc beep register 26 table 12 ? analog mixer input gain register 26 table 13 ? record select control registers 27 table 14 ? record gain registers 28 table 15 ? general purpose register 28 table 16 ? 3d control register 29 table 17 ? powerdown status register 30 table 18 ? low power modes 30 table 19 ? cold reset 32 table 20 ? warm reset 33 table 21 ? clocks 34 table 22 ? data setup and hold 35 table 23 ? signal rise and fall times 36 table 24 ? ac-link low power mode timing 37 table 25 ? ate test mode 37 table 26 ? operating conditions 38 table 27 ? power consumption 39 table 28 ? ac-link static specifications 39 table 29 ? 9704 analog performance characteristics 40 table 30 ? 9707 analog performance characteristics 42 table of contents ? figures figure 1 ? package outline 5 figure 2 ? STAC9704 block diagram 6 figure 3 ? connection diagram 7 figure 4 ? STAC9704/07 ac?97 link 11 figure 5 ? ac?97 bi-directional audio frame 14 figure 6 ? ac-link audio output frame 15 figure 7 ? start of an audio output frame 15 figure 8 ? STAC9704 /07 audio input frame 18 figure 9 ? start of an audio input frame 18 figure 10 ? STAC9704 powerdown timing 20 figure 11 ? STAC9704 /07 mixer functional diagram 22 figure 12 ? example of STAC9704 /07 powerdown/ powerup flow 31 figure 13 ? STAC9704 /07 powerdown/powerup with analog still alive 31 figure 14 ? cold reset 32 figure 15 ? warm reset 33 figure 16 ? clocks 34 figure 17 ? data setup and hold 35 figure 18 ? signal rise and fall times 36 figure 19 ? ac-link low power mode timing 36 figure 20 ? ate test mode 37
sigmatel, inc STAC9704/7 5 10/02/98 figure 1 ? package outline sigmatel STAC9704/7 48 pin tqfp a d1 d e e1 e 38 26 14 2 table 1 - package dimensions key 9704/7 dimension tqfp d 9.00 mm d1 7.00 mm e 9.00 mm e1 7.00 mm a (lead width) 0.20 mm e (pitch) 0.50 mm thickness 1.4 mm table 2 - pin designation pin # signal name pi n # signal name pin # signal name pin # signal name 1 dvdd1 13 phone 25 avdd1 37 mono_out 2 xtl_in 14 aux_l 26 avss1 38 avdd2 3 xtl_out 15 aux_r 27 vref 39 lnlvl_out_l 4 dvss1 16 video_l 28 vrefout 40 nc 5 sdata_out 17 video_r 29 afilt1 41 lnlvl_out_r 6 bit_clk 18 cd_l 30 afilt2 42 avss2 7 dvss2 19 cd_gnd 31 nc 43 nc 8 sdata_in 20 cd_r 32 cap2 44 nc 9 dvdd2 21 mic1 33 nc 45 nc 10 sync 22 mic2 34 nc 46 nc 11 reset# 23 line_in_l 35 line_out_l 47 nc 12 pc_beep 24 line_in_r 36 line_out_r 48 nc # denotes active low
sigmatel, inc. STAC9704/7 6 10/02/98 figure 2 . STAC9704 block diagram the STAC9704/7 block diagram, above, illustrates its primary functional blocks. it performs fixed 48k sample rate d-a & a-d conversion, mixing, and analog processing. the digital interface communicates with the ac?97 controller via the five wire ac-link and contains the 64 word by 16-bit registers. two fixed 48kss dac?s support a stereo pcm-out channel which contains a mix generated in the ac?97 controller of all software sources, including the internal synthesizer and any other digital sources. the mixer block mixes the pcm-out with any analog sources, then outputs to line_out and lnlvl_out. the mono_out delivers either mic only or a mono mix of sources from the mixer. the two fixed 48ks adc?s take any mix of mono or stereo sources , and convert it to a stereo pcm-in signal. all adcs and dacs operate at 18-bit resolution. the STAC9704/7 is designed primarily to support stereo, 2-speaker pc audio. however, multi-channel encoded stereo can be played out through the line_out and lnlvl_out. this encoded signal can be played on normal stereo speakers, or sent to consumer equipment or other decoding devices via line_out and lnlvl_out to an analog input connection for multi-channel playback. as an option, the STAC9704/07 provides for a stereo enhancement feature, sigmatel surround 3d (ss3d). ss3d provides the listener with several options to expand the soundstage beyond the normal 2-speaker arrangement. together with the logic component (controller) of ac?97, STAC9704/7 can be soundblaster a and windows a sound system compatible. soundblaster a is a registered trademark of creative labs. windows a is a registered trademark of microsoft corporation. line_out mono_out mic1 mic2 m u x mixer analog mixing and gain control dac dac adc adc power management digital interface registers 64 x 16 bits mic boost 0/20 db pcm out dacs pcm in adcs ac-link 4 stereo sources 2 mono sources mono stereo 48kss 48kss sync bit_clk sdata_out sdata_in reset lnlvl_out
sigmatel, inc. STAC9704/7 7 10/02/98 figure 3 - connection diagram ? see appendix a for an alternative connection diagram when using separate supplies . see appendix b for specific connection requirements prior to operation . video_l video_r aux_l afilt1 afilt2 avss1 avss2 dvss1 dvss2 avdd1 avdd2 dvdd1 dvdd2 ferrite bead * 2 ohm * 0.1uf 10uf 10uf 0.1uf 0.1uf 0.1uf 560 to 1000 pf 560 to 1000 pf 29 30 14 17 16 25 38 1 9 7 4 42 26 3 2 cap2 xtl_out xtl_in 3.3v or 5v +/-10% 24.576mhz 32 0.1uf 10uf sigmatel STAC9704/7 28 vrefout vref 27 10uf 0.1uf 33pf 33pf line_out_l line_out_r mono_out 35 36 37 line_in_r 24 line_in_l 23 phone 13 p c _ b e e p 12 mic2 22 aux_r 15 mic1 21 6 5 8 11 10 sdata_out sdata_in reset sync bit_clk cd_gnd cd_r 20 19 18 cd_l brd analog gnd brd digital gnd note: pins 31, 33, 34, 40, 43 - 48 are no connects * suggested ** teminate ground plane as close to power supply as possible lnlvl_out_l lnlvl_out_r 39 41
sigmatel, inc. STAC9704/7 8 10/02/98 1 . pin/signal descriptions 1.1 digital i/o these signals connect the STAC9704/7 to its ac?97 controller counterpart and an external crystal. table 3 . digital signal list signal name type description reset # i ac?97 master h/w reset xtl_in i 24.576 mhz crystal xtl_out o 24.576 mhz crystal sync i 48 khz fixed rate sample sync bit_clk o 12.288 mhz serial data clock sdata_out i serial, time division multiplexed, ac?97 input stream sdata__in o serial, time division multiplexed, ac?97 output stream # denotes active low
sigmatel, inc. STAC9704/7 9 10/02/98 1.2 analog i/o these signals connect the STAC9704/7 to analog sources and sinks, including microphones and speakers. table 4 . analog signal list signal name type description pc-beep i pc speaker beep pass through phone i from telephony subsystem speakerphone (or dlp - down line phone) mic1 i desktop microphone input mic2 i second microphone input line-in-l i line in left channel line-in-r i line in right channel cd-l i cd audio left channel cd-gnd i cd audio analog ground cd-r i cd audio right channel video-l i video audio left channel video-r i video audio right channel aux-l i aux left channel aux-r i aux right channel line-out-l o line out left channel line-out-r o line out right channel mono-out o to telephony subsystem speakerphone (or dlp ? down line phone)
sigmatel, inc. STAC9704/7 10 10/02/98 lnlvl_out_l o true line level out left channel lnlvl_out_r o true line level out right channel * note: any unused input pins should have a capacitor (1 uf suggested) to ground. 1.3 filter and voltage references these signals are connected to resistors, capacitors, or specific voltages. table 5 . filtering and voltage references signal name type description vref o reference voltage vrefout o reference voltage out 5ma drive (intended for mic bias) afilt1 o anti-aliasing filter cap - adc channel afilt2 o anti-aliasing filter cap - adc channel cap2 o adc reference cap
sigmatel, inc. STAC9704/7 11 10/02/98 1.4 power and ground signals table 6 . power signal list STAC9704/7 signal name type STAC9704 stac9707 avdd1 i analog vdd = 5.0v analog vdd = 3.3v avdd2 i analog vdd = 5.0v analog vdd = 3.3v avss1 i analog gnd analog gnd avss2 i analog gnd analog gnd dvdd1 i digital vdd = 5.0v or 3.3v digital vdd = 3.3v dvdd2 i digital vdd = 5.0v or 3.3v digital vdd = 3.3v dvss1 i digital gnd digital gnd dvss2 i digital gnd digital gnd 2. ac-link below is the figure of the ac-link point to point serial interconnect between the STAC9704/7 and its companion controller. all digital audio streams and command/status information are communicated over this ac-link. please refer to the ?digital interface? section 3 for details. figure 4. STAC9704/7? s ac97-link to its companion controller sync bit_clk sdata_out sdata_in reset digital dc?97 controller STAC9704/7 xtal_in xtal_out
sigmatel, inc. STAC9704/7 12 10/02/98 2.1 clocking STAC9704/7 derives its clock internally from an externally connected 24.576 mhz crystal or an oscillator through the xtal_in pin. synchronization with the ac?97 controller is achieved through the bit_clk pin at 12.288 mhz (half of crystal frequency). the beginning of all audio sample packets, or ?audio frames?, transferred over ac-link is synchronized to the rising edge of the ?sync? signal driven by the ac?97 controller. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled by the receiving side on each immediately following falling edge of bit_clk. 2.2 reset there are 3 types of resets as detailed under ?timing characteristics?. 1. a ?cold? reset where all STAC9704/7 logic and registers are initialized to their default state 2. a ?warm? reset where the contents of the STAC9704/7 register set are left unaltered 3. a ?register? reset which only initializes the STAC9704/7 registers to their default states after signaling a reset to the STAC9704/7, the ac?97 controller should not attempt to play or capture audio data until it has sampled a ?codec ready? indication via register 26h from the STAC9704/7. for proper reset operation , sdata_out should be ?0? during ?cold? reset. 3. digital interface 3.1 ac-link digital serial interface protocol the STAC9704/7 communicates to the ac?97 controller via a 5 pin digital serial interface called ac- link, which is a bi-directional, fixed rate, serial pcm digital stream. all digital audio streams, commands and status information are communicated over this point to point serial interconnect. this link handles multiple inputs, and output audio streams, as well as control register accesses using a time division multiplexed (tdm) scheme. the ac?97 controller synchronizes all ac-link data transaction. the following data streams are available on the STAC9704/7:
sigmatel, inc. STAC9704/7 13 10/02/98 pcm playback 2 output slots 2 channel composite pcm output stream pcm record data 2 input slots 2 channel composite pcm input strea m control 2 output slots control register write port status 2 input slots control register read port synchronization of all ac-link data transactions is signaled by the ac?97 controller. the STAC9704/7 drives the serial bit clock onto ac-link. the ac?97 controller then qualifies with a synchronization signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac- link data, STAC9704/7 for outgoing data and ac?97 controller for incoming data, samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a ?1? in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is ?tagged? invalid, it is the responsibility of the source of the data, ( STAC9704/7 for the input stream, ac?97 controller for the output stream), to stuff all bit positions with 0?s during that slot?s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the ?tag phase?. the remainder of the audio frame where sync is low is defined as the ?data phase?. additionally, for power savings, all clock, sync, and data signals can be halted. figure 5 . ac?97 standard bi-directional audio frame outgoing streams incoming streams sync slot # tag phase 0 1 2 3 4 5 6 7 8 9 10 11 12 tag cmd adr cmd data pcm left pcm rt na rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd na na pcm left pcm rt status data status adr tag data phase
sigmatel, inc. STAC9704/7 14 10/02/98 3.1.1 ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9704/7 dac inputs, and control registers. each audio output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the ?valid frame? bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by the STAC9704/7 indicate which of the corresponding 12 times slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac-link at its fixed 48khz audio frame rate. the following diagram illustrates the time slot based ac-link protocol. figure 6 . ac-link audio output frame sync bit_clk sdata_out valid frame slot1 slot2 end of previous audio frame slot(12) "0" "0" "0" 19 "0" "0" "0" 19 19 19 "0" data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the STAC9704/7 samples the assertion of sync. this following edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the ac?97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the STAC9704/7 on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
sigmatel, inc. STAC9704/7 15 10/02/98 figure 7 : start of an audio output frame sync bit_clk sdata_out stac9701 samples first sdata_out bit of frame here stac9701 samples sync assertion here valid frame slot1 slot2 end of previous audio frame sdata_out?s composite stream is msb justified (msb first) with all non-valid slots? bit positions stuffed with 0?s by the ac?97 controller when mono audio sample streams are sent from the ac?97 controller, it is necessary that both left and right sample stream time slots be filled with the same data. 3.1.1.1 slot 1: command address port the command port is used to control features, and monitor status (see audio input frame slots 1 and 2) of the STAC9704/7 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). the control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. audio output frame slot 1 communicates control register address, and write/read command information to the STAC9704/7 . command address port bit assignments : bit (19) read/write command (1= read, 0=write) bit (18:12) control register index (64 16-bit locations, addressed on even byte boundaries) bit (11:0) reserved (stuffed with 0's) the first bit (msb) sampled by STAC9704/7 indicates whether the current control transaction is a read or a write operation. the following 7 bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must he stuffed with 0's by the ac'97 controller.
sigmatel, inc. STAC9704/7 16 10/02/98 3.1.1.2 slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by slot 1, bit 19) bit (19:4) control register write data (stuffed with 0's if current operation is a read) bit (3 :0) reserved (stuffed with 0's) if the current command port operation is a read then the entire slot time must be stuffed with 0's by the ac'97 controller. 3.1.1.3 slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical ?games compatible" pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is transferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 3.1.1.4 slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical ?games compatible" pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20-bits is transferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 3.1.1.5 slots 5-12: reserved audio output frame slots 5-12 are reserved for future use and are always stuffed with 0's by the ac'97 controller. 3.1.2 ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac'97 controller. as is the case for audio output frame, each ac-link audio input frame consists of 12, 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure.
sigmatel, inc. STAC9704/7 17 10/02/98 within slot 0 the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether the STAC9704/7 is in the "codec ready" state or not. if the ?codec ready? bit is a 0, this indicates that STAC9704/7 is not ready for normal operation. this condition is normal following the de-assertion of power on reset, for example, while STAC9704/7 ?s voltage references settle. when the ac-link "codec ready" indicator bit is a 1, it indicates that the ac-link and STAC9704/7 control/status registers are in a fully operational state. the ac'97 controller must further probe the powerdown control status register (refer to mixer register section) to determine exactly which subsections, if any, are ready. prior to any attempts at putting STAC9704/7 into operation the ac'97 controller should poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that STAC9704/7 has become "codec ready". once the STAC9704/7 is sampled "codec ready", the next 12 bit positions sampled by the ac'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. the following diagram illustrates the time slot based ac-link protocol. figure 8 : STAC9704/7 audio input frame sync bit_clk sdata_in valid frame slot1 slot2 end of previous audio frame slot(12) "0" "0" "0" 19 "0" "0" "0" 19 19 19 "0" data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) a new audio input frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, STAC9704/7 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the STAC9704/7 transitions sdata_in into the first bit position of slot 0 ("codec ready" bit). each new bit position is presented to ac-link on a rising edge of bit_clk and subsequently sampled by the ac'97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
sigmatel, inc. STAC9704/7 18 10/02/98 figure 9 : start of an audio input frame sync bit_clk sdata_in STAC9704 samples first sdata_out bit of frame here STAC9704 samples sync assertion here codec ready slot1 slot2 end of previous audio frame sdata_in's composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by STAC9704/7 . sdata_in data is sampled on the falling edges of bit_clk. 3.1.2.1 slot 1: status address port the status port is used to monitor status for STAC9704/7 functions including, but not limited to, mixer settings, and power management. audio input frame slot 1?s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ?valid? by STAC9704/7 during slot 0) status address port hit assignments: bit (19) reserved (stuffed with 0) bit (18;12) control register index (echo of register index for which data is being returned) bit (11:0) reserved (stuffed with 0's) the first bit (msb) generated by STAC9704/7 is always stuffed with a 0. the following 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0's by STAC9704/7 .
sigmatel, inc. STAC9704/7 19 10/02/98 3.1.2.2 slot 2: status data port the status data port delivers 16-bit control register read data. bit (19:4) control register read data (stuffed with 0's if tagged "invalid") bit (3 :0) reserved (stuffed with 0's) if slot 2 is tagged "invalid" by STAC9704/7, then the entire slot will be stuffed with 0's. 3.1.2.3 slot 3: pcm record left channel audio input frame slot 3 is the left channel output of STAC9704/7 input mux, post-adc. STAC9704/7 adcs are implemented to support 18-bit resolution. STAC9704/7 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. 3.1.2.4 slot 4: pcm record right channel audio input frame slot 4 is the right channel output of STAC9704/7 input mux, post-adc. STAC9704/7 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. 3.1.2.5 slots 5-12: reserved audio input frame slots 5-12 are reserved for future use and are always stuffed with 0's. 3.2 ac-link low power mode the STAC9704/7 ?s ac-link can be placed in the low power mode by programming register 26h to the appropriate value. sdata_in is held at a logic low voltage level. the bit_clk is held at logic high after slot 2, in violation of the ac97 spec i fication. this issue is detailed in the STAC9704 errata, and has not caused customer problems. the ac?97 controller can wake up the STAC9704/7 by providing the appropriate reset signals.
sigmatel, inc. STAC9704/7 20 10/02/98 figure 10 . STAC9704/7 powerdown timing sync bit_clk sdata_out per frame sdata_in slot2 tag write to data slot2 tag per frame 0x20 pr4 note: bit_clk not to scale bit_clk and sdata_in are transitioned low immediately (within the maximum specified time) following the decode of the write to the powerdown register (26h) with pr4. when the ac?97 controller driver is at the point where it is ready to program the ac-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). the ac?97 controller should also drive sync, and sdata_out low after programming the STAC9704/7 to this low power mode. 3.2.1 waking up the ac-link once the STAC9704/7 has halted bit_clk, there are only two ways to ?wake up? the ac-link. both methods must be activated by the ac?97 controller. the ac-link protocol provides for a ?cold ac?97 reset?, and a ?warm ac?97 reset?. the current power down state would ultimately dictate which form of reset is appropriate. unless a ?cold? or ?register? reset (a write to the reset register) is performed, wherein the ac?97 registers are initialized to their default values, registers will keep their current state during all power down modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. when ac-link powers up it indicates readiness via the codec ready bit (input slot 0, bit 15).
sigmatel, inc. STAC9704/7 21 10/02/98 cold reset - a cold reset is achieved by asserting reset# for the minimum specified time. by driving reset# low, bit_clk, and sdata_in will be activated, or re-activated as the case may be, and all STAC9704/7 control registers will be initialized to their default power on reset values. note: reset# is an asynchronous input. # denotes active low warm reset - a warm reset will re-activate the ac-link without altering the current STAC9704/7 register values. a warm reset is signaled by driving sync high for a minimum of 1 us in the absence of bit_clk. note: within normal audio frames, sync is a synchronous input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the STAC9704/7 .
sigmatel, inc. STAC9704/7 22 10/02/98 4. STAC9704/7 mixer the STAC9704/7 mixer is designed to the ac?97 specification to manage the playback and record of all digital and analog audio sources in the pc environment. these include: system audio : digital pcm input and output for business, games and multimedia cd/dvd : analog cd/dvd-rom redbook audio with internal connections to codec mixer mono microphone : choice of desktop mic, with programmable boost and gain speakerphone : use of system mic and speakers for telephone, dsvd, and video conferencing video : tv tuner or video capture card with internal connections to codec mixer aux/synth : analog fm or wavetable synthesizer, or other internal source figure 11 . STAC9704/7 mixer functional diagram vol mute pcm out d/a phone line in line_out cd video aux analog audio sources mono_out pcm in 20db master volume mono volume a/d a/d master input volume s s mux mux vol vol vol vol vol vol vol mute mute mute mute mute mute mute key mono analog stereo analog digital lnlvl_out lnlvl volume 3d 3d -6db -6db pc_beep mic1 mic2 s
sigmatel, inc. STAC9704/7 23 10/02/98 table 8 . mixer functional connections source function connection pc_beep pc beep pass thru from pc beeper output phone speakerphone or dlp in from telephony subsystem mic1 desktop microphone from mic jack mic2 second microphone from second mic jack line_in external audio source from line-in jack cd audio from cd-rom cable from cd-rom video audio from tv tuner or video camera cable from tv or vidcap card aux upgrade synth or other external source internal connector pcm out digital audio output from ac?97 controller ac-link line_out stereo mix of all sources to output jack lnlvl_out additional stereo mix of all sources to output jack mono_out mic or mix for speakerphone or dlp out to telephony subsystem pcm in digital audio input to ac?97 controller ac-link
sigmatel, inc. STAC9704/7 24 10/02/98 4.1 m ixer input the mixer provides recording and playback of any audio sources or output mix of all sources. the STAC9704/7 supports the following input sources: any mono or stereo source mono or stereo mix of all sources 2-channel input w/mono output reference (mic + stereo mix) note: any unused input pins must have a capacitor (1 uf suggested) to ground. 4.2 mixer output the mixer generates two distinct outputs: a stereo mix of all sources for output to the line_out a stereo mix of all sources for output to the lnlvl_out a mono, mic only or mix of all sources for mono_out * note: mono output of stereo mix is attenuated by 6 db . 4.3 pc beep implementation pc beep is active on power up and defaults to an unmuted state. during active reset# , pc_beep is passed through the codec to line_out. the user should mute this input before using any other mixer input because the pc beep input can contribute noise to the lineout during normal operation.
sigmatel, inc. STAC9704/7 25 10/02/98 4.4 mixer registers: table 9. mixer registers reg # name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 de fault 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 na 02h master volume mute x x ml4 ml3 ml2 ml1 ml0 x x x mr4 mr3 mr2 mr1 mr0 8000h 04h lnlvl volume mute x x ml4 ml3 ml2 ml1 ml0 x x x mr4 mr3 mr2 mr1 mr0 8000h 06h master volume mono mute x x x x x x x x x x mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute x x x x x x x x x x pv3 pv2 pv1 pv0 x 0000h 0ch phone volume mute x x x x x x x x x x gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute x x x x x x x x 20db x gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute x x gl4 gl3 gl2 gl1 gl0 x x x gr4 gr3 gr2 gr1 gr0 8808h 1ah record select x x x x x sl2 sl1 sl0 x x x x x sr2 sr1 sr0 0000h 1ch record gain mute x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 8000h 20h general purpose x x 3d x x x mix ms lpbk x x x x x x x 0 000h 22h 3d control x x x x x x x x x x x x x x dp1 dp0 0 000h 26h powerdown ctrl/stat pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 000fh 7ch vendor id1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 na 7eh vendor id2 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 na notes: 1. all registers not shown and bits containing an x are reserved. 2. any reserved bits, marked x, can be written to but are don?t care upon read back. 3. pc_beep default to 0000h, mute off. 4. if opti onal bits d13, d5 of register 02h or d5 of register 06h are set to 1, then the corresponding attenuation is set to 46db and the register reads will produce 3fh as a value for this attenuation/gain block.
sigmatel, inc. STAC9704/7 26 10/02/98 4.4.1 reset register (index 00h) writing any value to this register performs a register reset, which causes all registers to revert to their default values. reading this register returns the id code of the part. 4.4.2 play master volume registers (index 02h, 04h, and 06h) these registers manage the output signal volumes. register 02h controls the stereo master volume (both right and left channels), register 04h controls the optional stereo true line level out, and register 06h controls the mono volume output. each step corresponds to 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml5 through ml0 is for left channel level, mr5 through mr0 is for the right channel and mm5 through mm0 is for the mono out channel. the default value is 8000h (1000 0000 0000 0000), which corresponds to 0 db attenuation with mute on. table 10 : play master volume register m ute m x 5 ?mx0 function r ange 0 00 0000 0db attenuation req. 0 01 1111 46.5 attenuation req. 1 xx xxxx db attenuation req. 4.4.3 pc beep register (index 0ah) this register controls the level for the pc beep input. each step corresponds to approximately 3 db of attenuation. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. pc_beep supports motherboard implementations. the intention of routing pc_beep through the STAC9704/7 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. in order for this to be viable the pc_beep signal needs to reach the output jack at all times. note: the pc_beep is recommended to be routed to l & r line outputs even when the STAC9704/7 is in a reset state. this is so that power on self test (post) codes can be heard by the user in case of a hardware problem with the pc. for further pc_beep implementation details please refer to the ac?97 technical faq sheet. the default value can be 0000h or 8000h, which corresponds to 0 db attenuation with mute off or on.
sigmatel, inc. STAC9704/7 27 10/02/98 table 11 : pc_beep register mute pv3?pv0 function 0 0000 0 db attenuation 0 1111 45 db attenuation 1 xxxx db attenuation 4.4.4 analog mixer input gain registers (index 0ch - 18h) th ese registers control the gain/attenuation for each of the analog inputs. each step corresponds to approximately 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. register 0eh (mic volume register) has an extra bit that is for a 20db boost. when bit 6 is set to 1, the 20 db boost is on. the default value is 8008, which corresponds to 0 db gain with mute on. the default value for the mono registers is 8008h, which corresponds to 0db gain with mute on. the default value for stereo registers is 8808h, which corresponds to 0 db gain with mute on. table 12 : analog mixer input gain register mute gx4?gx0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 -34.5 db gain 1 xxxxx - db gain 4.4.5 record select control register (index 1ah ) used to select the record source independently for right and left. the default value is 0000h, which corresponds to mic in.
sigmatel, inc. STAC9704/7 28 10/02/98 table 13 : record select control registers sr2?sr0 right record source 0 mic 1 cd in (right) 2 video in (right) 3 aux in (right) 4 line in (right) 5 stereo mix (right) 6 mono mix 7 phone sl2?sl0 left record source 0 mic 1 cd in (l) 2 video in (l) 3 aux in (l) 4 line in (l) 5 stereo mix (l) 6 mono mix 7 phone
sigmatel, inc. STAC9704/7 29 10/02/98 4.4.6 record gain registers (index 1ch ) the 1ch register adjusts stereo input record gain . each step corresponds to 1.5 db. 22.5 db corresponds to 0f0fh and 000fh respectively. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel(s) is set at - db. the default value is 8000h, which corresponds to 0 db gain with mute on. table 14 : record gain registers mute gx3? gx0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxx - gain 4.4.7 general purpose register (index 20h) this register is used to control some miscellaneous functions. below is a summary of each bit and its function. the ms bit controls the mic selector. the lpbk bit enables loopback of the adc output to the dac input , without involving the ac-link, allowing for full system performance measurements. table 15 : general purpose register bit function 3d 3d stereo enhancement on/off 1 = on mix mono output select 0 = mix, 1= mic ms mic select 0 = mic1, 1 = mic2 lpbk adc/dac loopback mode
sigmatel, inc. STAC9704/7 30 10/02/98 4.4.8 3d control register (index 22h) this register is used to control the 3d stereo enhancement function, sigmatel surround 3d (ss3d), built into the ac'97 component. note the register bits, dp1 ? dp0, are used to control the separation ratios in the 3d control. ss3d provides for a wider soundstage extending beyond the normal 2-speaker arrangement. note that the 3d bit in the general purpose register (20h) must be set to 1 to enable ss3d functionality and for the bits in 22h to take effect. table 16 : 3d control registers dp1 ? dp0 separation ratio 0 0 3 (default) 0 1 3 (low) 1 0 4.5 (med.) 1 1 6 (high) 3 separation ratios are implemented as shown above. the separation ratio defines a series of equations that determine the amount of depth difference (high, medium, and low) perceived during two-channel playback. the ratios provide for options to narrow or widen the soundstage. 4.4.9 powerdown control/status register (index 26h) this read/write register is used to program powerdown states and monitor subsystem readiness. the lower half of this register is read only status, a ?1? indicating that the subsection is ?ready?. ready is defined as the subsection?s ability to perform in its nominal state. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. when the ac-link ?codec ready? indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac?97 control and status registers are in a fully operational state. the ac?97 controller must further probe this powerdown control/status register to determine exactly which subsections, if any are ready.
sigmatel, inc. STAC9704/7 31 10/02/98 table 17 : powerdown status register bit function ref vref?s up to nominal level anl analog mixers, etc. ready dac dac section ready to playback data adc adc section ready to playback data 5. low power modes the STAC9704/7 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). there are 7 commands of separate power down . the power down options are listed in table 1 8 . the first three bits , pr0..pr2, can be used individually or in combination with each other , and control power distribution to the adc ?s, dac?s and mixer . the last analog power control bit , pr3 , affects analog bias and refer e nce voltages , and can only be used in combination with pr1, pr2 , and pr3 . pr3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. pr0 and pr1 control the pcm adc?s and dac?s only. pr2 a n d pr3 do not need to be "set" before a pr4, but pr0 and pr1 must be "set" before pr4. table 18 : low power modes grp bits function pr0 pcm in adc?s & input mux powerdown pr1 pcm out dacs powerdown pr2 analog mixer powerdown (vref still on) pr3 analog mixer powerdown (vref off) pr4 digital interface (ac-link) powerdown (extnl clk off) pr5 internal clk disable
sigmatel, inc. STAC9704/7 32 10/02/98 pr6 not implemented figure 12 : example of STAC9704/7 powerdown/powerup flow pr0=1 pr1=1 pr2=1 pr4=1 default normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off coda-link pr0=0 & adc=1 pr1=0 & dac=1 pr2=0 & anl=1 warm reset cold reset ready =1 the above figure illustrates one example procedure to do a complete powerdown of STAC9704/7 . from normal operation, sequential writes to the powerdown register are performed to power down STAC9704/7 a piece at a time. after everything has been shut off, a final write (of pr4) can be executed to shut down the ac-link. the part will remain in sleep mode with all its registers holding their static values. to wake up, the ac?97 controller will send an extended pulse on the sync line , issuing a warm reset. this will restart the ac-link (resetting pr4 to zero). the STAC9704/7 can also be woken up with a cold reset. a cold reset will reset all of the registers to their default states. when a section is powered back on, the powerdown control/status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. figure 13: STAC9704/7 powerdown/powerup flow with analog still alive pr0=1 pr1=1 pr4=1 normal adcs off pr0 dacs off pr1 digital i/f off pr4 shut off coda-link pr0=0 & adc=1 pr1=0 & dac=1 warm reset the above figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this configuration can be used when playing a cd (or external line_in source) through STAC9704/7 to the speakers , while most of the system in low power mode. the procedure for this follows the previous except that the analog mixer is never shut down.
sigmatel, inc. STAC9704/7 33 10/02/98 6. testability the STAC9704/7 has two test modes. one is for ate in-circuit test and the other is restricted for sigmatel?s internal use. STAC9704/7 enters the ate in circuit test mode if sdata_out is sampled high at the trailing edge of reset#. once in the ate test mode, the digital ac-link outputs (bit_clk and sdata_in) are driven to a high impedance state. this allows ate in-circuit testing of the ac?97 controller. this case will never occur during standard operating conditions. once either of the two test modes have been entered, the STAC9704/7 must be issued another rest with all ac-link signals held low to return to the normal operating mode.
sigmatel, inc. STAC9704/7 34 10/02/98 7. ac timing characteristics (t ambient = 25 c, avdd = dvdd = 5.0v or 3.3v 5 %, avss=dvss+0v; 50pf external load) 7.1 cold reset figure 14 : cold reset reset# bit_clk tres_low trst2clk table 19 : cold reset parameter symbol min typ max units reset# active low pulse width tres_low 1.0 - - us reset# inactive to bit_clk startup delay trst2clk 162.8 - - ns # deno tes active low. 7.2 warm reset as per the STAC9704 errata, the bit_clk is triggered on the rising edge of the sync pulse rather than the falling edge of the sync pulse as specified in the ac97 specification. this issue is not known to have caused any customer problems. figure 15 : warm reset sync bit_clk tsync_2clk tsync_high
sigmatel, inc. STAC9704/7 35 10/02/98 table 20 : warm reset parameter symbol min typ max units sync active high pulse width tsync_high - 1.3 - us sync inactive to bit_clk startup delay tsync _ 2clk 162.8 - - ns 7.3 clocks figure 16 : clocks bit_clk sync tclk_high tclk_low tclk_period tsync_low tsync_high tsync_period table 21 : clocks parameter symbol min typ max units bit_clk frequency - 12.288 - mhz bit_clk period tclk_period - 81.4 - ns bit_clk output jitter - - 750 ps blt_clk high pulsewidth (note 1) tclk_high 32.56 40.7 48.84 ns bit_clk low pulse width (note 1) tclk_low 32.56 40.7 48.84 ns sync frequency - 48.0 - khz sync period tsync_period - 20.8 - us sync high pulse width tsync_high - 1.3 - us sync low_pulse width tsync_low - 19.5 - us notes: 1) worst case duty cycle restricted to 40/60.
sigmatel, inc. STAC9704/7 36 10/02/98 7.4 data setup and hold (50pf external load) figure 17 : data setup and hold bit_clk sdata_in sdata_out sync tsetup thold tsetup thold table 22 : data setup and hold parameter symbol min typ max units setup to falling edge of bit_clk tsetup 15.0 - - ns hold from falling edge of bit_clk thold 5.0 - - ns note 1: setup and hold time parameters for sdata_in are with respect to the ac?97 controller.
sigmatel, inc. STAC9704/7 37 10/02/98 7.5 signal rise and fall times - (50pf external load; from 10% to 90% of vdd) figure 18 : signal rise and fall times bit_clk sdata_in triseclk tfallclk trisedin tfalldin table 23 : signal rise and fall times parameter symbol min typ max units bit_clk rise time triseclk 2 - 6 ns bit_clk fall time tfallclk 2 - 6 ns sdata_in rise time trisedin 2 - 6 ns sdata_in fall time tfalldin 2 - 6 ns 7.6 ac-link low power mode timing bit_clk stops high in violation of the ac97 specification as noted on the STAC9704 /07 errata, but this condition has not caused any known customer problems. figure 19 : ac-link low power mode timing sync bit_clk sdata_out sdata_in don't care slot 1 slot 2 write to data 0x20 pr4 note: bit_clk not to scale ts2_pdown
sigmatel, inc. STAC9704/7 38 10/02/98 table 24 : ac-link low power mode timing parameter symbol min typ max units end of slot 2 to bit_clk, sdata_in low ts2_pdown - 14 15 us 7.7 ate test mode figure 20 : ate test mode reset# sdata_out sdata_in, bit_clk toff hi-z tsetup2rst table 25 : ate test mode parameter symbol min typ max units setup to trailing edge of reset# (also applies to sync) tsetup2rst 15.0 - - ns rising edge of reset# to hi-z delay toff - - 25.0 ns notes: 1. all ac-link signals are normally low through the trailing edge of reset#. bringing sdata_out high for the trailing edge of reset# causes STAC9704/7 ?s ac-link outputs to go high impedance which is suitable for ate in circuit testing. 2. once either of the two test modes have been entered, the STAC9704/7 must be issued another reset# with all ac-link signals low to return to the normal operating mode. # denotes active low.
sigmatel, inc. STAC9704/7 39 10/02/98 8. electrical specifications: 8.1 absolute maximum ratings: voltage on any pin relative to ground vss - 0.3v to vdd + 0.3v operating temperature 0 o c to 70 o c storage temperature -55 o c to +125 o c soldering temperature 260 o c for 10 seconds output current per pin 4 ma except vrefout = 5ma 8.2 recommended operating conditions table 26 . operating conditions parameter min typ max units power supplies + 3. 3v digital + 5v digital + 5v analog + 3.3v analog 3. 135 4. 7 5 4. 7 5 3. 135 3.3 5 5 3.3 3. 435 5. 2 5 5. 2 5 3. 435 v v v v ambient temperature 0 - 70 o c sigmatel reserves the right to change specifications without notice.
sigmatel, inc. STAC9704/7 40 10/02/98 8.3 power consumption table 27 . power consumption parameter min typ max units digital supply current + 5v digital + 3. 3v digital 45 4 ma ma analog supply current + 5v analog 70 ma + 3. 3v analog 62 ma power down status in sequence pr0 + 5v analog supply current pr1 + 5v analog supply current pr2 + 5v analog supply current pr3 + 5v analog supply current pr4 +3. 3v digital supply current pr4 + 5v digital supply current pr5 no effect 58 44 20 0.1 0.1 0.1 ma ma ma ma ma ma 8.4 ac-link static digital specifications (t ambient = 25 o c, dvdd = 5.0v or 3.3v 5 %, avss=dvss = 0v; 50pf external load) table 28. ac-link static specifications parameter symbol min typ max units input voltage range vin -0.30 dvdd + 0.30 v low level input range vil - - 0.30xdvdd v high level input voltage vih 0.40xdvdd - - v high level output voltage voh 0.50xdvdd - - v low level output voltage vol - - 0.2xdvdd v input leakage current (ac-link inputs) - -10 - 10 ua output leakage current (hi-z?d ac-link outputs) - -10 - 10 ua output buffer drive current - - 4 ma
sigmatel, inc. STAC9704/7 41 10/02/98 8.5 STAC9704 analog performance characteristics (t ambient = 25 o c, avdd = 5.0v 5 %, dvdd = 3.3v 5%, avss=dvss = 0v; 1 khz input sine wave; sample frequency = 48 khz; 0db = 1 vrms, 10k ohm/ 50pf load, testbench characterization bw: 20 hz ? 20khz, 0db settings on all gain stages ) table 29 . analog performance characteristics parameter min typ max units full scale input voltage: line inputs mic inputs 1 - - 1.0 0.1 - - vrms full scale output voltage: line output 5v - 1.0 - vrms analog s/n: cd to line_out 5v other to line_out 5v 90 - 98 98 - - db analog frequency response 2 20 - 20,000 hz digital s/n 3 d/a 5v a/d 5v 85 75 96 87 - - db total harmonic distortion: line output 4 - - 0.02 % d/a & a/d frequency response 5 20 - 19,200 hz transition band 19,200 - 28,800 hz stop band 28,800 - hz stop band rejection 6 +85 - - db out-of-band rejection 7 - +40 - db group delay - - 1 ms power supply rejection ratio (1khz) - +40 - db crosstalk between input channels - - -70 db spurious tone rejection - +100 - db attenuation, gain step size - 1.5 - db input impedance 10 - - k ohm input capacitance - 15 - pf
sigmatel, inc. STAC9704/7 42 10/02/98 vrefout - 0.41 x avdd - v interchannel gain mismatch adc 0.5 db interchannel gain mismatch dac - 0.5 db gain drift 100 ppm/ o c dac offset voltage 10 50 mv deviation from linear phase 1 degree external load impedance 10 k ohm mute attenuation (vrms input) 90 96 db notes: 1. with +20 db boost on, 1.0vrms with boost off 2. 1 db limits 3. the ratio of the rms output level with 1 khz full scale input to the rms output level with all zeros into the digital input. measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 4. 0 db gain, 20 khz bw, 48 khz sample frequency 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output.
sigmatel, inc. STAC9704/7 43 10/02/98 8.6 stac9707 analog performance ch aracteristics (t ambient = 25 o c, avdd = dvdd = 3.3v 5 %, avss=dvss = 0v; 1 khz input sine wave; sample frequency = 48 khz; 0db = 1 vrms, 10k ohm/ 50pf load, testbench characterization bw: 20 hz ? 20khz, 0db settings on all gain stages) table 30. analog performance characteristics parameter min typ max units full scale output voltage: line inputs to line output 3.3v line inputs to line_out 3.3v @ line in = 1 vrms and @ gain setting of -6 db line inputs to line_out 3.3v @ line in = 0. 5 vrms and @ gain setting of 0db pcm to line_out 3.3v @ full scale pcm input @pcm gain setting of 0db pcm to line output 3.3v mic inputs to line_out 3.3v @ mic in = 1 vrms and @ gain setting of 0db - 0. 5 0. 5 0. 5 0. 5 0.5 - vrms vrms vrms vrms vrms analog s/n: cd to line_out 3.3v other to line_out 3.3v - 90 90 - analog frequency response 2 20 - 20,000 hz digital s/n 3 d/a 3.3v a/d 3.3v 85 75 90 85 - - total harmonic distortion: line output 4 - - 0.02 % d/a & a/d frequency response 5 20 - 19,200 hz transition band 19,200 - 28,800 hz stop band 28,800 - hz stop band rejection 6 +85 - - db out-of-band rejection 7 - +40 - db group delay - - 1 ms power supply rejection ratio (1khz) - +40 - db crosstalk between input channels - - -70 db
sigmatel, inc. STAC9704/7 44 10/02/98 spurious tone rejection - +100 - db attenuation, gain step size - 1.5 - db input impedance 10 - - k ohm input capacitance - 15 - pf vrefout - 0.41 x avdd - v interchannel gain mismatch adc 0.5 db interchannel gain mismatch dac - 0.5 db gain drift 100 ppm/ o c dac offset voltage 10 50 mv deviation from linear phase 1 degree external load impedance 10 k ohm mute attenuation (0 db) 90 96 db notes: 1. with +20 db boost on, 1.0vrms with boost off 2. 1 db limits 3. the ratio of the rms output level with 1 khz full scale input to the rms output level with all zeros into the digital input. measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 4. 0 db gain, 20 khz bw, 48 khz sample frequency 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output.
sigmatel, inc. STAC9704/7 45 10/02/98 appendix a split independent power supply operation in pc applications, one power supply input to the STAC9704/7 may be derived from a supply regulator (as shown in figure 3) and the other directly from the pci power supply bus. when power is applied to the pc, the regulated supply input to the ic will be applied some time delay after the pci power supply. without proper on- chip partitioning of the analog and digital circuitry, some manufacturer ?s codec s would be subject to on-chip scr type latch-up. sigmatel?s STAC9704/7 specifically allows power-up sequencing delays between the analog (avddx) and digital (vdddx) supply pins. these two power supplies can power-up independently and at different rates with no adverse effects to the codec. the ic is designed with independent analog and digital circuitry that prevents on-chip scr type latch-up. video_l video_r aux_l afilt1 afilt2 avss1 avss2 dvss1 dvss2 avdd1 avdd2 dvdd1 dvdd2 0.1uf 10uf 10uf 0.1uf 0.1uf 0.1uf 560 to 1000 pf 560 to 1000 pf 29 30 14 17 16 25 38 1 9 7 4 42 26 3 2 cap2 xtl_out xtl_in 3.3v or 5v +/-10% 24.576mhz 32 0.1uf 10uf sigmatel STAC9704/7 28 vrefout vref 27 10uf 0.1uf 33pf 33pf line_out_l line_out_r mono_out 35 36 37 line_in_r 24 line_in_l 23 phone 13 p c _ b e e p 12 mic2 22 aux_r 15 mic1 21 6 5 8 11 10 sdata_out sdata_in reset sync bit_clk cd_gnd cd_r 20 19 18 cd_l brd analog gnd brd digital gnd note: pins 31, 33, 34, 40, 43 - 48 are no connects ** teminate ground plane as close to power supply as possible lnlvl_out_l lnlvl_out_r 39 41 reg 3.3v or 5v +/-10% *avdd must always be >= dvdd
sigmatel, inc. STAC9704/7 46 10/02/98 appendix b +5.0v/+3.3v power supply operation notes the STAC9704 is capable of operating from a single 5v supply connected to both dvdd and avdd. even though the STAC9704 has digital switching levels of 0.2vdd to 0.5vdd (see ac link electrical characteristics in this data book), we recommend that all digital interface signals to the ac-link be 5v. if digital interface signals below 5v are used, then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity . the STAC9704 can also operate from a 3.3v digital supply connected to dvdd while maintaining a 5v analog supply on avdd. on-chip level shifters ensure accurate logic transfers between the analog and digital portions of the STAC9704 . if digital interface signals above 3.3v are used (i.e. a +5v ac-link interface) , then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-chip esd protection diodes from turning on. (see appendixes a concerning split independent power supply operation ). the stac9707 must be run from a 3.3v supply connected to both dvdd and avdd. if digital interface signals above 3.3v are used (i.e. a +5v ac-link interface) , then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-ship esd protection diodes from turning on. *always operate the stac97xx digital supply from the same supply voltage as the digital controller supply. *all the analog inputs must be ac-coupled with a capacitor of 3.3 uf or greater. it is recommended that a resistor of about 47k ohm be connected from the signal side of the capacitor to analog gnd as shown below. *all the analog outputs must be ac-coupled. if an external amplifier is used, make sure that the input impedance of the amplifier is at least 10k ohm and use an ac-coupling capacitor of 3.3 uf. 47k > 3.3 uf signal analog input
sigmatel, inc. STAC9704/7 47 10/02/98 - notes -
sigmatel, inc. STAC9704/7 48 10/02/98 - note -
sigmatel, inc. STAC9704/7 49 10/02/98 for more information, please contact: sigmatel, inc. 6101 w. courtyard dr., bldg. 1, suite 100 austin, texas 78730 tel (512) 343-663 6, fax (512) 343-6199 email: sales @sigmatel.com homepage: www. s igmatel .com

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